As the line widths and cell sizes of semiconductor memory devices have been progressively scaled down, many researchers have focused on developing a memory device that can operate at low power supply voltage. Hence, a layout technology that can provide functions required for low operation voltage conditions is necessary.
Currently, an internal voltage generator that generates an internal voltage after being supplied with an external power supply voltage is installed within a semiconductor memory device to provide a voltage necessary for the operation of the semiconductor memory device. In those memory devices using bit line amplifiers such as dynamic random access memories (DRAMs), a core voltage is a voltage corresponding to a logic high of a data signal.
Once a group of word lines selected by a row address is activated, voltages corresponding to respective stored data of multiple memory cells that are connected to the selected word lines are supplied to bit lines, and the bit line amplifiers sense the voltages supplied to the bit lines and amplify the sensed voltages. Thus, many of the bit line amplifiers operate simultaneously to amplify the voltages supplied to the bit lines. However, a large amount of current is dissipated from a terminal of the core voltage that drives the bit line sense amplifiers, and a core voltage level decreases. When the core voltage level continues to decrease, it is often difficult to amplify the voltages supplied to the bit lines for a short period using the core voltage. In other words, the sensing rates of the bit lines become decreases.
Hence, during an initial stage of operating the bit line sense amplifiers (i.e., after the memory cells and the bit lines share charges), the bit line sense amplifiers sense and amplify the voltages amplified to the bit lines using a higher voltage (typically an external power supply voltage VDD) than the core voltage. This method is often called “over driving mode.”
FIG. 1 illustrates a simplified diagram of a typical control circuit for a bit line sense amplifier block BLSA.
The bit line sense amplifier block BLSA includes a pull up power line RTO and a pull down power line SB. First to third driver transistors M1, M2 and M3 are provided to drive the pull up power line RTO and the pull down power line SB. The second driver transistor M2 is used to drive the pull up power line RTO using a core voltage VCORE in response to a pull up power line driving control signal SAP. The third driver transistor M3 is to drive the pull down power line SB using a ground voltage VSS in response to a pull down power line driving control signal SAN. In response to an over driving signal OVDP, the first driver transistor M1 supplies an external power supply voltage VDD to the pull up power line RTO through the second driver transistor M2.
An over driving signal generation block generates the over driving signal OVDP in response to an active command ACT. The first and second driver transistors M1 and M2 may be replaced with P-type channel metal-oxide semiconductor (PMOS) transistors.
Supplying the active command ACT activates word lines, and data stored in cells are transferred to respective bit line pairs. After a certain period, the pull up power line driving control signal SAP and the pull down power line driving control signal SAN are activated as a logic high level. At this time, the over driving signal OVDP that has activated as a logic high level in response to the active command ACT before the activation of the pull up power line driving control signal SAP and the pull down power line driving control signal SAN instructs the over driving of the pull up power line RTO for a predetermined period. More specifically, when the pull up power line driving control signal SAP, the pull down power line driving control signal SAN and the over driving signal OVDP are activated as the logic high level, the first to third driver transistors M1, M2 and M3 are turned on to drive the pull down power line RTO using the external power supply voltage VDD and to drive the pull up power line SB using the ground voltage VSS.
After the elapse of a certain time, the over driving signal OVDP is inactivated as a logic low level, and thus, the first driver transistor M1 is turned off and the pull up power line RTO is driven using only the core voltage VCORE.
FIGS. 2A to 2C illustrate graphs of voltage level changes in a terminal of a core voltage VCORE according to operation conditions for a bit line sense amplifier block in a time basis.
Particularly, FIG. 2A illustrates a graph of the voltage level change in the core voltage terminal during operation of the bit line sense amplifier block that does not perform a bit line over driving operation. After an active command ACT0 is supplied, the voltage level of the core voltage terminal drops down abruptly. For reference, if an external power supply voltage VDD applied to DRAMs has a specific range between 1.7 V and 1.9 V, a semiconductor memory device should operate normally not only at a range of the external power supply voltage VDD between 1.7 V to 1.9 V, but also at a range of the external power supply voltage VDD less than 1.7 V or greater than 1.9 V but up to a certain level.
FIG. 2B illustrates a graph of the voltage level change in the core voltage terminal during operation of the bit line sense amplifier block that performs the bit line over driving operation under the condition of low external power supply voltage VDD. Due to the over driving operation, the core voltage terminal can maintain a stabilized voltage level.
FIG. 2C illustrates a graph of the voltage level change in the core voltage terminal during operation of the bit line sense amplifier block that performs the bit line over driving operation under the condition of high external power supply voltage VDD. Since a voltage difference between the core voltage VCORE and the external power supply voltage VDD is large, performing the over driving operation in response to the active commands ACT0 and ACT1 causes a voltage level of the core voltage terminal to increase abruptly. Also, when active commands are input consecutively, the voltage level of the core voltage VCORE increases further due to the charges remaining in the core voltage terminal in response to the precedent active command.
In such a case, the selected word line is driven using a high voltage VPP, which is an internal voltage higher than the external power supply voltage VDD, and the bit line has an over driving voltage whose level is higher than a normal level of the core voltage VCORE. As a result, in a cell transistor having a gate connected to a word line and a source connected to a bit line, a voltage Vgs between the gate and the source of the cell transistor is usually reduced. The reduction in the gate-source voltage Vgs of the cell transistor may impair reliability of a read or write operation, and thus, a semiconductor memory device may operate erroneously.